Frame conversion circuit including initial value input circuit

ABSTRACT

A frame conversion circuit for changing data with different speeds to the same speed to thereby obtain data of the same frame length is provided with an initial value inputting circuit for writing an arbitrary initial value into a memory at each address each time data is sequentially read out according to a read address signal from the memory. Therefore, no error is produced in a sign bit check and the possibility of occurrence of erroneous synchronization is minimized. The initial value inputting circuit may be implemented using a plurality of pull-up resistors connected to a data bus.

This application is a continuation of U.S. application Ser. No.07/542,098, filed Jun. 22, 1990, now abandoned.

BACKGROUND OF THE INVENTION

The present invention relates to a frame conversion circuit fordemultiplexing various incoming multiplexed signals that have beentransmitted over a high-speed communication line and then converting thedemultiplexed signals into the same frames thereby making the speeds ofthe various data signals uniform.

In digital transmission systems, in general, several pieces ofinformation are transmitted after being multiplexed in order to achieveeffective use of the transmission medium and greater economy in thetransmission. Such multiplexing is performed based on time. One periodof the multiplexed signal is called a frame and the multiplexing methodis called time-division multiplexing. A plurality of low order groupdigital signals are time-divisionally multiplexed by a multiplexer intohigh order group digital signals before transmission over the high-speedcommunication line. Thus, a greater number of channels are transmittedover the same link. These signals are transmitted from one exchange toanother by a suitable transmission means capable of accommodating thenecessary number of channels, and thereby transmitted to a destination.Upon arrival at the destination, the high order group digital signalsare separated into low order group digital signals by a demultiplexer.

Specifically, in a system like the Integrated Services Digital Network(ISDN), various data such as general data, speech signals, and videosignals are transmitted after being multiplexed at different speeds.Therefore, a process for demultiplexing these multiplexed signals withdifferent speeds is required. Hence, a frame conversion circuit addsredundant bits to the lower speed signals, thereby providing them withthe same speed as the higher speed signals.

A representative example of prior art frame conversion circuits will bedescribed below with reference to FIG. 1 and FIG. 2. When data (A, B,and C in FIG. 2) are input from a high speed communication line to atristate buffer 12, the tristate buffer 12 and a tristate buffer 16 areenabled and simultaneously, address signals, generated in a randompattern (3, 1, and 4 in FIG. 2) for indicating addresses at which thedata should be written into a memory 11, are output from a write addressgenerator 14. The data are written into the memory according to theseaddress signals. At this time, each random address signal corresponds toa kind of data. Upon completion of the writing of the data into thememory, a tristate buffer 17 is enabled and, at the same time,sequential address signals (1, 2, 3, 4, 5, 6 in FIG. 2) are output froma read address generator 15, and thereupon, data (B, -, A, C, -, - inFIG. 2) are read out from the memory according to these address signals.Here, "-" represents a frame stored in the memory previously or anindefinite frame.

A sign bit adding/checking portion 18 includes a cyclic redundancycheck. It adds sign bits to the rearmost position of the data written inthe memory, and at the time it monitors the sign bits thereby checkingwhether the data is properly transmitted and received. By repeating suchrandom writing of data into the memory according to the kinds of data,sequentially addressing the addresses in memory and reading the datafrom the memory, the frame conversion for arranging various data ofdifferent speeds into high speed signals having a uniform speed isperformed.

In the above-described conventional frame conversion circuit, when datawas written into the memory according to random address signals and,then, sequentially read out, there remained data that had previouslybeen written at the addresses where data was not written this time.Hence, the previous data will also be read out as indicated by obliquelines in FIG. 3. When the read out data are processed in such case, itsometimes occurs that the system becomes unable to recognize theposition where the currently processed data is located. In such anevent, confirmation of the data is achieved by synchronizing the data bymeans of the synchronization bits within the frames. But, if old datahas remained and the data are by some chance taken as thesynchronization bits, then erroneous synchronization or malfunctionoccurs, which has been a problem in the prior art.

Further, when data are read out from the memory in the initial stage, ifthere is any address in the memory at which no data was input earlier,the indefinite data read out from the region at that address will bewithout any sign bits attached thereto, and therefore, errors will beproduced when the sign bit is checked as shown in FIG. 4, which has alsobeen a problem in the prior art.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a frameconversion circuit in which no error will be produced during the signbit check step.

Another object of the present invention is to provide a highly reliableframe conversion circuit in which data, which would cause erroneoussynchronization, will not be included in the read out data.

In accordance with an aspect of the present invention, there is provideda frame conversion circuit including: write address generation means forgenerating a random address signal and for writing an incomingtransmitted data signal into a memory; means for adding sign bits to thedata to be written into the memory and for checking the sign bits at thetime when the data is read out from the memory; read address generationmeans for generating sequential address signals for addressing addressesin the memory sequentially based on the sequential address signals, andfor reading the data from each address in the memory; and initial valueinput means for writing an arbitrary initial value into the memory ateach address each time the data is read out of the memory sequentiallyaccording to the read address signal.

Preferably, the initial value input means is formed of plural pull-upresistors connected in parallel with plural output lines of a tristatebuffer to which the transmitted signal is input.

The above and other objects, features and advantages of the presentinvention and the manner of realizing them will become more apparent,and the invention itself will best be understood, from a study of thefollowing description and appended claims, with reference to theattached drawings showing some preferred embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a general structure of a prior artframe conversion circuit;

FIG. 2 is a time chart associated with the operation of the frameconversion circuit of FIG. 1;

FIG. 3 and FIG. 4 are explanatory drawings for explaining problems inthe prior art frame conversion circuit;

FIG. 5 is a block diagram showing an embodiment of the presentinvention;

FIG. 6 is a block diagram showing an embodiment of the presentinvention; and

FIG. 7 is a time chart associated with the embodiment shown in FIG. 6.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

First, the principle of the frame conversion circuit of the presentinvention will be briefly described below with reference to FIG. 5. Inthe block diagram of FIG. 5, parts similar to or corresponding to thosein the prior art frame conversion circuit shown in FIG. 1 are denoted bythe same reference numerals and explanation of the same is omitted here.As is apparent by comparing FIG. 5 with FIG. 1, the frame conversioncircuit of the present invention differs from the prior art frameconversion circuit only in that it is provided with an initial valueinputting circuit 19. Addresses in the memory are sequentially addressedand each time data is read out from each address of the memory accordingto a read address signal. The initial value inputting circuit 19 writesan arbitrary initial value into the memory at the address from which thedata is read out. The initial value is preferably "all 1s" or "all 0s".Since, such an initial value is written, each time data is read out,into the memory at the address from which the data is read out, an errordoes not occur during a sign bit check and erroneous synchronization isalso prevented from occurring.

Referring now to FIG. 6, an embodiment of the frame conversion circuitof the present invention will be described below. The frame conversioncircuit of the present embodiment is, for example, a 24-multiframestructure in an octet multiplexing method with one frame having a lengthof an octet and, hence, there are eight output lines of the tristatebuffer 12. The write address generator 14 in FIG. 5 is a counter 22 anda ROM 21 and the read address generator 15 is a counter 20. In the ROM21, there are stored write addresses corresponding to the kinds of datasuch as general data and speech data to be written into the memory 11,and the random patterns of the address signals generated therefrom arechanged by a switching signal generated by a controller, not shown,according to the kinds of data to be written into the memory 11. Forexample, when the data is general data, the address signals are outputin the random pattern of 3, 2, 6 in binary numbers to the addressesdesignated by the binary numbers, whereas, in the case of speech data,the address signals are output in the random pattern of 4, 1, 6 to theaddresses designated by the binary numbers. More specifically, theaddress signals output from the ROM 21 become different random patternsdepending on the kind of data even when the signal from the counter isthe same. For example, when the output of the counter 22 is 1, theaddress signal is 3 if the switching signal indicates that the datawritten into the memory 11 is general data, whereas it is 4 if theswitching signal indicates that data is speech data. The read counter 20outputs the count value in a binary number to the memory 11. The counter22 is reset each time data is read out from the memory 11, while thecounter 20 is reset each time data is written into the memory 11. Thetristate buffers 12, 16, and 17 are controlled by control signals (R/Wsignals) from the controller, not shown, so that they area brought intoan enabled state or a disabled state.

Below will be described the operation of the present embodiment withreference to the time chart of FIG. 7. When speech data A, B, and C areinput to the tristate buffer 12, the count value of the counter 22 isinput to the ROM 21 and, at the same time, a switching signal is inputto the ROM 21, whereby address signals for speech data are generated bythe ROM 21. Upon the control signal (R/W signal) going High to tristatebuffer 12, the tristate buffer 12 is brought into the enabled state. Atthe same time, the tristate buffer 16 is also brought into the enabledstate. Then a sign bit is added to the input data output from thetristate buffer 12 by the sign bit adding/checking circuit 18 and theinput data with the sign bit attached thereto are written into thememory 11 according to the address signals from the ROM 21 (3, 1, and 4in FIG. 7) and a write enable signal. After the described operations arerepeated several times, the data A, B, and C are written into the memoryat the designated addresses.

Upon completion of the writing of data into the memory 11, the tristatebuffer 17 is brought into the enabled state, and the count values of thecounter 20 are output in binary numbers to the memory 11. Since thesecounted values become the read address signals (1, 2, 3, 4, 5, and 6 inFIG. 7), data are read out from the memory 11 sequentially according tothese read address signals and an output enable signal. At this time, asign bit check is simultaneously performed by the sign bitadding/checking circuit 18. The read out data are latched by theflip-flop circuit 13 according to a latch timing signal and, then, areoutput therefrom. The output lines of the tristate buffer 12 are heldHigh by the initial value inputting circuit 19, each time a data readingoperation is performed, so that a set of sign bits is added to the databy the sign bit adding/checking circuit 18 according to the addresssignal at the time of the reading, and data of "all 1s" is written intothe memory 11 at each address. Accordingly, after all the data are readout from the memory 11, the memory is in an "all 1s+sign bit" state.

Therefore, there are no indefinite frames in the memory 11, but thepattern of "all 1s" which has a very low probability of causingerroneous synchronization or malfunction, is written into memory. Hence,reliability of the frame conversion circuit can be improved. Further,data is always written in the memory 11 at all of the addresses inmemory, so that no error occurs during the sign bit check.

The initial value inputting circuit 19 includes pull-up resistorsconnected to the eight output lines of the tristate buffer 12. When theoutput of the tristate buffer 12 is in the high impedance state (R/Wsignal is low), the output lines are held High. Therefore, the initialvalues input by the initial value inputting circuit 19 in the presentembodiment become "all 1s". When the tristate buffer 12 is in the enablestate (R/W signal is High) and the output data signal is Low, then, evenif the output lines are pulled up by the pull-up resistors of theinitial value inputting circuit 19, the output lines go Low since theoutput lines are grounded through the ground within the tristate buffer12. Thus, the input signal to the tristate buffer 12 is the output ofthe tristate buffer 12.

What is claimed is:
 1. A frame conversion circuit comprising:means forreceiving a variety of types of data signals from a data bus, each datasignal having data elements; means for adding a sign bit to the dataelements of the received data signals; write address means forgenerating a random address signal, based on the type of data signal,and for writing the data elements of each data signal into memorylocations, based on the random address signal; read address generationfor generating a sequential address signal to address the memorylocations sequentially, for reading each data element from each memorylocation, based on the sequential address signal, and for checking thesign bit of each data element as each data element is read out; andinitial value input means for writing an arbitrary initial value intoeach memory location as each data element corresponding to each memorylocation is read out.
 2. The frame conversion circuit according to claim1, wherein the initial value input means comprises a plurality ofpull-up resistors, each connected to the data bus.
 3. The frameconversion circuit according to claim 1, further comprising a flip-flopcircuit, connected to the read means and the data bus, which, inresponse to a latch timing signal which indicates when the flip-flopcircuit should latch data read out by the read means, outputs latcheddata to the data bus.
 4. The frame conversion circuit according to claim1, wherein the arbitrary initial value written into each memory locationcomprises plural bits of a common bit value and a sign bit.
 5. The frameconversion circuit of claim 4, wherein the common bit value is "1".